The semiconductor industry has been advanced in an ever brisk pace, recently. In order to achieve high performance integrated circuits or high package density of a wafer, the sizes of semiconductor devices have become smaller and smaller than before in the field of Ultra Large Scale Integrated (ULSI) technologies.
Integrated circuits includes more than millions devices in a specific area of a wafer and electrically connecting structure for connecting these devices to perform desired function. One of the typical devices is metal oxide semiconductor field effect transistor (MOSFET). The MOSFET has been widely, traditionally applied in the semiconductor technologies. As the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues to fabricate them. The typically issue that relates to hot carriers injection is overcame by the development of lightly doped drain (LDD) structure.
Further, the requirement of the devices towards high operation speed and low operation power. For deep sub-micron meter MOS devices, the self-aligned silicide (SALICIDE) contact, ultra-shallow source and drain junction are used for improving the operation speed and short channel effect as seen in reference "Silicided Silicon-Sidewall Source and Drain (S.sup.4 D) structure for high-performance 75-nm gate length p MOSFETs, T. Yoshitomi et al., 1995, Symposium on VLSI Technology Digest of Technical papers". The highly doped silicon sidewall converted with silicide film are used as a part of source and drain. The extension of the source and drain is produced by the solid-phase diffusion of boron from the highly doped silicon sidewall. In another research by T. Yoshitomi, he develops a high performance CMOS with good control of short channel effect and silicide resistance. Please see "High Performance 0.15 .mu.m Single Gate Co Salicide CMOS, T. Yoshitomi et al., 1996, Symposium on VLSI Technology Digest of Technical papers". The CoSi.sub.2, NiSi have been used for deep sub-micron high speed CMOS due to the low sheet resistance of fine silicide line. However, it is difficult to make ultra-shallow junction and form SALICIDE contact without degrading the device performance.
The requirement of the ULSI CMOS technology is the need of devices operated at low supply voltage and they have high speed. When the supply-voltage is reduced, the threshold voltage needs to be scaled down to achieve the desired circuit switching speed. IBM has proposed that CMOS employs non-uniform channel doping profiles and ultra-shallow source and drain extensions and halos, which can be referenced in "CMOS technology scaling 0.1 .mu.m and beyond, IBM semiconductor research and development center, Bijan Davari, 1996, IEDM, 96-555". For the high performance case, the threshold voltage is scaled down less than the supply voltage in order to maintain a reasonable standby current.
Further, in order to achieve the low voltage operation with small threshold voltage, the surface channel PMOSFET with the p+ polysilicon gate has been investigated in place of the buried channel with the n+ polysilicon gate due to the superior short channel behavior. Unfortunately, the effect of boron penetration through the thin gate oxide into Si substrate will degrade the device performance. Prior art approaches to overcome these problems have resulted in the development of stacked-amorphous-silicon (SAS) film to suppress the boron penetration into ultra-thin gate oxide. As seen in "Suppression of Boron Penetration into an Ultra-Thin Gate Oxide by Using a Stacked-Amorphous-Silicon (SAS) Film, Shye Lin Wu, 1993, IEDM, p. 329". In this paper, Wu suggests that the use of stacked-amorphous-silicon (SAS) can suppress the boron penetration through an ultra-thin oxide. The SAS gate capacitor exhibits a smaller flat-band voltage shift, a less charge trapping and interface state generation rate than those of the as-deposited poly-Si gate capacitor. The main reason of the suppression of the boron or fluorine penetration by using SAS is because that the SAS structure exhibits the dopant segregation at the stacked-Si boundaries and a longer path for dopant diffusion to the interface between silicon and oxide.